
DS3106
29
Table 7-11. T4 APLL Frequency Configuration
T4 APLL
FREQUENCY
(MHz)
T4 APLL DFS
FREQUENCY
(MHz)
T4 APLL
FREQUENCY
MODE
T4APT0
SETTING IN
T4FREQ[3:0]
SETTING IN
T0FT4[2:0]
SETTING IN
OUTPUT
JITTER
(pk-pk, ns, typ)
Disabled
77.76
Squelched
0
0000
XXX
< 0.5
311.04
77.76
77.76MHz
0
0001
XXX
< 0.5
98.304
24.576
12 x E1
0
0010
XXX
< 0.5
131.072
32.768
16 x E1
0
0011
XXX
< 0.5
148.224
37.056
24 x DS1
0
0100
XXX
< 0.5
98.816
24.704
16 x DS1
0
0101
XXX
< 0.5
274.944
68.736
2 x E3
0
0110
XXX
< 0.5
178.944
44.736
DS3
0
0111
XXX
< 0.5
100.992
25.248
4 x 6312kHz
0
1000
XXX
< 0.5
250.000
62.500
GbE
÷ 16
0
1001
XXX
< 0.5
122.880
30.720
3 x 10.24
0
1010
XXX
< 0.5
160.000
40.000
4 x 10
0
1011
XXX
< 0.5
104.000
26.000
2 x 13
0
1100
XXX
< 0.5
98.304
24.576
T0 12 x E1
1
XXXX
000
< 0.5
250.000
62.500
T0 GbE
÷ 16
1
XXXX
001
< 0.5
131.072
32.768
T0 16 x E1
1
XXXX
010
< 0.5
148.224
37.056
T0 24 x DS1
1
XXXX
100
< 0.5
98.816
24.704
T0 16 x DS1
1
XXXX
110
< 0.5
100.992
25.248
T0 4 x 6312kHz
1
XXXX
111
< 0.5
Table 7-12. OC3 and OC6 Output Frequency Selection
AOF BIT
FREQUENCY
OC3
OC6
0
0000
Disabled
0
0001
2kHz
0
0010
8kHz
0
0011
Digital2
T0 / 2
0
0100
Digital1
0
0101
T0 / 48
T0 / 1
0
0110
T0 / 16
0
0111
T0 / 12
0
1000
T0 / 8
0
1001
T0 / 6
0
1010
T0 / 4
0
1011
T4 / 64
0
1100
T4 / 48
0
1101
T4 / 16
0
1110
T4 / 8
0
1111
T4 / 4
1
0000
Disabled
1
0001
T0 / 64
T4 / 5
1
0010
T4 / 20
T4 / 2
1
0011
T4 / 12
T4 / 1
1
0100
T4 / 10
T02 / 5
1
0101
T4 / 5
T02 / 2
1
0110
T4 / 2
T02 / 1
Note 1: The value of the OFREQn field (in t
he OCR2 and OCR3 registers) corresponding to output clock OCn.